Ingénieur Vérification Asic R&D H/F - Ile-de-France - Eviden

    Eviden
    Eviden Ile-de-France

    il y a 1 semaine

    Description
    Dans le cadre de développement d'ASIC de types contrôleur réseau, routeur, contrôleur de cohérence de cache et processeur à destination des serveurs haut de gamme et haute performance Bull (serveurs « big data » et « exascale »), la mission consiste à participer à la vérification d'un ASIC complexe en utilisant les méthodologies de vérification fonctionnelle « Constraint-Random, Coverage Driven » sous-jacentes au standard de vérification UVM. Vos missions : * Acquérir la connaissance de l'architecture et la microarchitecture de l'ASIC en étudiant les spécifications et en interagissant avec les équipes d'architecture et de design logique. * Rédaction des spécifications de vérification. * Rédaction des plans de test en étroite collaboration avec l'équipe design logique. * Développement des environnements de vérification (UVM-SystemVerilog/C++), les tests et les modèles de couverture * Suivre, analyser et debugger les erreurs de simulation. * Suivre et analyser les résultats couverture des simulations pour améliorer les tests en conséquence et ainsi atteindre les objectifs de couverture dans les délais impartis.

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