- Exploring techniques for memory mapped IO operations to access external devices (DDR, SPI Flash, HyperRAM) whilst improving data throughput within the system.
- Developing innovative hardware algorithms and processes for parallelizing external memory access in a multi core and distributed computing environment. Study innovation in terms of scatter-gather techniques and bandwidth, and propose improvement through data compression and decompression or other methods.
- Propose a set of hardware algorithms to be implemented in HDL and provide associated Models.
- Code in RTL and implant those algorithms in the already existing Test Chip vehicle.
- Conduct comparative study with RTL simulation, bandwidth measurement, listing advantages and disadvantages of each solution.
- Writing, defining and documenting the verification environment to find bugs in the design
- Understanding of the fundamentals of hardware architecture and design
- Knowledge of hardware description languages Verilog, SystemVerilog
- Knowledge of CPU interconnect protocols CHI, AXI, AHB, APB and OCP.
- Willingness to learn new skills. Highly motivated and a strong work ethic.
- Fluent oral and written English
- Proficiency in scripting languages, Python/Perl/TCL
- Familiarity with ARM architectures and instruction sets
- Experience with RTL and simulators
- Proficiency in software programming
- Experience of Unix development environment
- Good level of French would be advantageous
Concept/Design Intern - Sophia Antipolis, France - arm limited
Description
The Role
Job Overview:
ARM improves people's lives by spreading intelligence in electronic products that transform the way we live and work. ARM is indeed at the heart of the technologies of mobile communications, IoT, automotive, security and artificial intelligence (AI).
Arm Solutions Engineering group in Sophia Antipolis develops new System on Chip Test Chips Demonstrator combining the latest CPUs generation on the more sophisticated technology node (3nm). This internship will open the doors of the concept and design domain for SoC design and associated IPs.
Responsibilities:
Required Skills and Experience:
"Nice To Have" Skills and Experience:
In Return:
You will work directly with engineers across the company to build next-generation SoC, IPs and CPUs and will have a direct impact on our bottom line and the ability to deliver improvements for our customers. You will be part of a growing, fast-paced, and lively team, and keeping ownership for the implementation of your work
Working on interesting new projects is exciting, but we also know how meaningful it is to receive support. That's why throughout your internship, you can expect regular feedback and development opportunities, social activities to connect with your peers, an end of summer celebration, plus the opportunity to be *considered for future Graduate positions (*subject to performance). #getreadytogrow
Our program is crafted to give you the best start possible and support your personal growth as well as professional development.
Gain a competitive salary of 1900 Euros/month, supportive rewards package, alongside unparalleled learning and networking opportunities from the best in industry.
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