Pll Analog Ic Design Engineer and Technical Leader - Paris, France - SCALINX

SCALINX

Entreprise vérifiée

Paris, France

il y a 2 semaines

Posté par:

Sophie Dupont

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Job Title

Paris/Caen/Grenoble

- analog_tech_lead_PLL_2023_06
Work description

Focus on the architecture and design of high performance RF PLL.
Lead and support analog design workpackages from transistor schematic to GDSII
Participate, in close collaboration with the other project technical leaders, to the definition of the IC architecture and verification methodology.
Participate to discussion with customer on product architecture and specification definition.
Drive the architecture definition of the analog part(s) under his/her responsibilities.
Drive, in close collaboration with the analog design and layout team, the specifications of the IC analog subblocks to get the best area/power/performance tradeoff
Work in close collaboration with the layout team to define the floorplan strategy to meet the stringent performance (e.g. speed, matching ) requirements
Contribute to the design and verification methodology at chip level and subblocks level
Define the test strategy of the analog part(s) under his/her responsibilities and drive its implementation
Participate to the evaluation of the fabricated IC in our measurement lab
Work in team to successfully design a stateofthe art IC
Animate design reviews
Write documentation in accordance with company Quality Assurance policy

Qualification and Experience

You have a MSc or PhD in Electrical Engineering or equivalent and 10+ years of handson experience in chiplevel and circuitlevel architecture definition, transistor level design and verification
You have a solid background in low jitter LC based PLL design on integrated circuit for highspeed and highperformance ADC/DAC data converters.
You have string experience in PLL design in advanced node CMOS/FDSOI silicon technologies (22nm and beyond)
You have a very good vision of the entire analog/mixedsignal IC design flow from transistor schematic to GDSII
You have a strong experience in mixedsignal IC project and technical leader role
You have an experience in the design of highspeed, low noise and interference robust analog and mixedsignal circuit
You have solid knowledge of analog design and simulation tools (Cadence Spectre)
You are creative and proactive
You demonstrate good analytical and problemsolving skills
A strong experience with Cadence design flow is necessary
A strong experience with EM tools is necessary
You are a team player with a critical attitude and sense of initiative
You communicate fluently in English (oral and written)

How to apply