- Design, develop and continuously improve the FPGA prototyping workflow, integrating it into the company-wide HW and SW flows
- Generate, test and debug complex FPGA platforms from RTL, ensuring performance, robustness and maintainability
- Develop and integrate hardware and software blocks, as well as automation tools and scripts to improve productivity and user experience
- Provide expert-level technical support to internal users, analyze complex issues and propose long-term, scalable solutions
- Act as a primary technical interface with EDA tool vendors and IP providers, driving technical discussions and tracking issue resolution
- Contribute to technology watch, evaluate new tools and share best practices across teams
- Discovery interview with our Talent Acquisition Partner (30 min)
- AssessFirst personality test - no need to worry, there is no wrong or right answer; our goal is to see beyond your resume (45')
- Interview with one HRBP in order to answer to your last questions (30 min)
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We are building an entirely new team who will be using state of the art multi-FPGA prototyping platforms porting and modeling our entire design connecting it with real hardware. · ...
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Senior FPGA prototyping engineer - Maisons-Laffitte - SiPearl
Description
SiPearl is the European fabless designer of sovereign secure high-performance energy-efficient CPUs for HPC, AI and data centres. These CPUs will help address strategic challenges in the fields of security, defence, medical research, energy, climate and engineering with a reduced environmental footprint.
This new generation of microprocessors will first target EuroHPC Joint Undertaking ecosystem, which is deploying world-class supercomputing infrastructures in Europe for solving major challenges in medical research, artificial intelligence, security, energy management and climate with a reduced carbon footprint.
Incubated within the European Processor Initiative (EPI) consortium and seed-funded by the European Union, SiPearl employs almost 200 people in :
France (Maisons-Laffitte, Grenoble, Massy, Sophia Antipolis),
Spain (Barcelona)
and Italy (Bologna)
Following a €130 million Series A, the company has launched its Series B round.
About SiPearl…
SiPearl is the European fabless designer of sovereign secure high-performance energy-efficient CPUs for HPC, AI and data centres. These CPUs will help address strategic challenges in the fields of security, defence, medical research, energy, climate and engineering with a reduced environmental footprint.
In June 25, SiPearl completed the design of the most complex CPU ever designed in Europe, Rhea1. Featuring 80 Arm Neoverse V1 cores, with 61 billion transistors, it is currently in production at TSMC. Sipearl CPUs will equip the two first European exascale supercomputers belonging to EuroHPC JU: Rhea1 will be integrated into the JUPITER machine based in Germany and Rhea2 will be part of Alice Recoque in France.
Incubated within the European Processor Initiative (EPI) consortium and seed-funded by the European Union, SiPearl employs almost 200 people in :
France (Maisons-Laffitte, Grenoble, Massy, Sophia Antipolis),
Spain (Barcelona)
and Italy (Bologna)
Following a €130 million Series A, the company has launched its Series B round.
About the role
To validate our first tape-out, we developed an initial prototyping platform, using a smart hybrid approach, connecting a real hardware system development board (socket ready) with a small prototyping FPGA board.
Given the success and eager adoption of this approach by our Firmware team, we decided to think even bigger and build a full stack prototyping and demonstration platform, porting the full complexity of our designs to FPGA prototyping, and enabling the development of the entire FW and SW (BIOS, Kernel or high speed-interfaces like PCIe/DDR/UCIe) pre-silicon
To tackle that task, we are building an entire new team, who will be using state of the art multi-FPGA prototyping platforms (Ultrascale+ VP1902, the largest FPGAs in the industry), porting and modeling our entire design and connecting it with real hardware.
Your missions
What would make you succeed in this role
Strong expertise in FPGA development and prototyping on complex platforms
Solid knowledge of HDL languages (SystemVerilog, VHDL), timing constraints (SDC) and advanced design rules
Ability to architect robust solutions, take ownership of technical topics and drive continuous improvements
Professional proficiency in English within an international environment
Strong communication skills, team spirit and a high level of autonomy
Scientific rigor, curiosity, adaptability and a strong problem-solving mindset
Dear candidate, even if you consider you do not fulfill all the qualifications mentioned above, please still apply and share with us why you believe you would be a good fit.
Recruitment process
Benefits and conditions
Contract: Permanent Contract (CDI)
Benefits: annual bonus*; meal vouchers (60% covered by SiPearl); health insurance (70% covered by SiPearl); illimited access and pre-paid sessions with a practitioner of your choice on our mental health partner app, ; technical, linguistic and personal development training; BSPCE
Work model: On-Site or Hybrid (2 days/week remote)
Office: This role is open for our locations in France (Maisons-Laffitte, Massy, Grenoble and Sophia Antipolis), Spain (Castelldelfels - Barcelona)
Please note that while we do not provide VISA Sponsorship, we are committed to assisting international candidates with the visa application process to the best of our ability.
Are you curious to learn more about us?
Follow us on LinkedIn to stay updated with our latest news
Get updated about our recruiting activities: Sipearl careers webpage
Get to know a bit more about our team culture: Welcome to the jungle
At SiPearl, we are dedicated to building a diverse and inclusive workplace that thrives on the strength of varied perspectives and backgrounds. We recruit talent based on merit, experience, and alignment with our company's goals and values.
CDI Senior FPGA prototyping engineer
• Maisons-Laffitte, Île-de-France, .FR
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