SOC Design - Greater Paris Metropolitan Region - IC Resources

Description

I have an exciting and unique management position available in the cutting-edge semiconductor space.

Working for an established name in complex IP development, you will be responsible for managing a multi-skilled team of enginners with HW and SW backgrounds.

Applicants must have a broad range of SW and HW knowledge, to understand the architecture and development of exisiting and future IPs.

The position is based in Paris, so the 1st preference will be for French and Englisg bilingual speakers.

Applicants must have a deep understanding of IP and SOC architecture, managing digital design / verification teams, aswell as software development processes and their corresponding algorithms.

MUST HAVE experience:

• BSc / MSc / PhD in Electronics / Micro-Electronics / Electronic Engineering / Physics or similar related fields
• 10-20 years' industry experience in ASIC / FPGA hardware development
• Management / team leadership of teams of engineers
• Deep understanding of the ASIC / FPGA design flow
• Digital IC / IP design and architecture
• SOC architecture / SOC design / SOC system design / IP integration within a SOC
• SOC performance / optimisation
• RTL design - verilog or VHDL
• Verification languages - system verilog
• UVM environments
• Modelling - System C, TLM, UML etc
• Algorithms / fixed point / vectors / accelerators
• Git / GitHUb
• C++ / Python / TcL / Perl / Shel / Java

Desired knowledge:

• Significant experience in high-speed digital IP products - PCIe, Serdes, Ethernet
• Memory / cache coherency
• Large-scale processor based SOCs
• CPU / GPU / RISC-V
• Infrastructure / DevOps / CI / CD
• Design automation flows
• EDA tools

Keyword search:

• ASIC Manager, HW Manager, Hardware Manager, Digital Design Manager, Verification Manager, Team Lead,
• Systems manager / Software Manager / Tools Manager / SOC Manager / Automation Manager
• Modelling / architecture / performance / compiler
• HW-SW co-design
• AI applications
• Compute architecture
• R&D