- Acquire knowledge of the ASIC's architecture and microarchitecture by studying the specifications and collaborating with the architecture and design teams.
- Draft verification specifications and develop test plans in close collaboration with the design team.
- Create verification environments (using Verilog/System Verilog), tests, and coverage models for various platforms (RTL, PARTL, GLS).
- Monitor, analyze, and debug simulation errors.
- Track and analyze the simulation coverage results to improve tests accordingly and achieve coverage objectives within specified timelines.
- Lead the development and maintenance of verification design flows for ASIC projects, from architecture definition to physical implementation, aiming to minimize test time.
- Enhance internal verification expertise to consult, educate, and train design staff on verification requirements and how to prepare new designs for new projects.
- Provide support and guidance to clients for all verification activities.
- Provide internal support and guidance for design and verification activities. Participate in setting up and executing the project by working closely with project managers and other team members.
- Verification of complex SoC/ASICs and IPs.
- Proficiency in the UVM verification methodology.
- Experience in developing Constraint-Random/Coverage-Driven verification environments in System Verilog/C++ (including drivers/monitors, constrained random tests, self-checking checkers, and System Verilog-Cover group/SVA coverage models).
- Knowledge of simulation tools and coverage tracking.
- Efficiency in problem-solving through rapid identification of root causes and the development of fixes or workarounds.
- Experience in UPF design is a significant asset.
- Experience in RTL coding including design checks (CDC, RDC, coding rules) is a plus.
- Ability to positively and strategically influence the digital design team, with an eye towards improving overall product quality.
- Integrate a SME that benefits from the support of a group
- Salary package: fixed salary (depending on experience), profit-sharing, meal ticket card, shareholding plan, health insurance
- In the heart of a "green zone for grey matter", we encourage our employees to use soft mobility: €/km bicycle and scooter allowance, 60% reimbursement of the public transport subscription & bicycle rental, 300€ subsidy for the purchase of a bicycle (after 1 year of employment) and carpooling.
- Executive status, days of in lieu or banked hours
- Hybrid working model agreement for twenty days a year, or the possibility of regular or even full working for from depending on personal circumstances.
- And of course, the Welcome pack when you arrive
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Digital IC Verification Engineer - Meylan, France - Dolphin Design
Description
To support the growth of our ASIC business unit, we are seeking an experienced digital verification engineer (M/F) , based in Meylan (38).
Your role will consist of technically managing the verification activities from the specification to the startup of the chip on projects in the defense, aeronautics, or aerospace fields.
As the main point of contact in the company, this position involves technical support for pre- and post-sales customer activities and the deployment of state-of-the-art verification design flows and methodologies.
Thus, you will work at the interface with all necessary internal and external stakeholders.
You will be recognized as leading digital verification methodologies.
Missions:
1. Project Execution:
2. Methodology:
3. Client:
4. Project:
You're about to become a dolphin..
With a technical background in electrical engineering, computer engineering, computer science, or equivalent with 10 years of experience.
Applications from candidates with less experience will also be considered, so please do not hesitate to apply.
Benefits of becoming a Dolphin:
Is this role not an exact fit? to stay in touch, we'll let you know when we have new positions on the team.
Don't wait any longer, take the plunge
