Digital Verification Manager - Sophia Antipolis, France - NXP Semiconductors

NXP Semiconductors

Entreprise vérifiée

Sophia Antipolis, France

il y a 3 semaines

Posté par:

Sophie Dupont

beBee Recruiter

Description

The R&D organization's Digital Verification team, based in Mougins, supports products, as Multimedia processors, from the prototyping phase to production with a particular focus on digital functionality.

In this context, we are looking for a Digital Verification Manager n engineer with 10 years of experience in the field.

Responsibilities

Manager of a team of 10 engineers in Design Digital Verification, in charge of goals setting, performance tracking, promotion, etc.
Responsible for complete functional verification of Sub-System and SOC at all levels presilicon: RTL, PARTL, GLS, PAGLS
Define the verification strategy for the design as a function of its architecture, the expected use cases, the technology the limitations of the tools and the schedule constraints
Able to develop, debug, and modify test environments and test cases for different platforms (RTL, PARTL, GLS, PAGLS, Emulation)
Determine the quality of the verification by defining coverage goals and methods for measuring these goals.
Collaborate with Program Management Office and Design FE and BE managers

Profile

Minimum Master Degree (Bac +5)
Minimum 10 years of experience in IP or SoC design or verification.
Experience in management and program technical lead position
Good team spirit and collaboration driven
Knowledge of the architecture, elements and functionality of multimedia processor based SOCs (i.

MX, OMAP, EXYNOS), including CPUs, DMA, MMU, PLLS, memory and peripheral interfaces

Verification skills (test planning, testcase, testbench, simulation, debug) required.
Design skills (design documentation, RTL coding, synthesis, static and formal checkers, etc.) a plus.
Fluent in English and good communication skills required