Senior SOC Chip Lead - Sophia Antipolis, France - NXP Semiconductors

NXP Semiconductors

Entreprise vérifiée

Sophia Antipolis, France

il y a 2 semaines

Posté par:

Sophie Dupont

beBee Recruiter

Description

NXP is seeking a Chip Lead that will be responsible for all aspects of a SoC project.

This encompasses SoC definition and specification with Marketing / Architecture, planning with Program Management, IP selection, Integration, RTL coding, Verification, DFT, Physical Design including P&R, timing and power closure, Packaging, Validation and product ramp with Product and Test Engineering.

The Chip Lead
_is _the responsible party for any SoC, working with all functional leads to deliver the product from concept to production ramp.

Concept, Definition & Planning with Marketing, Architecture and Program Management

Requirement and architectural spec review and feature list finalization
Drive Feature Vs Die Size Vs Schedule tradeoff
Microarchitecture, Logic partitioning planning
Review requirements (safety, power, performance) Architects and Design team
Drive and coordinate NPI schedule planning (from Design side)

IP Interface

Work with Systems/Arch and IP team to finalize the IP specs
Working with IP team to align and integrate IP delivery schedules into overall NPI cycle
Managing IP trackers and realtime adjustment on SoC design execution wherever IP plans change from Baseline
Working as interface on SoC-IP interactions for closing all the feedback loops

Design Execution

Leading the design core team weekly.
Daytoday decision making with regard to micro architecture, verification, DFT, physical design etc
Management interface towards overall design execution
Managing SoC defects/development tickets for effective closure. Managing Errata for NPI.
Technical guidance and leadership to resolve complex issues arising during Design Execution or Silicon bring up
Driving all the QMS and Best Practices mandated reviews in various functions through functional leads
Schedule Planning & Management

Closure with Test Engineering

Reviewing Design Requirements for TEST with DFT/TE team
Identifying test optimization strategies along with TE team

Post Silicon Bring up support

Driving validation plan feedback from SoC design.
Managing design support for root causing of validation sightings and issues reported.

External Engagement

Single point of contact for Applications/FAE teams for any customer queries or support
Debug support for issues reported by customers to NXP
Handling various (Customer/ISO/IATF/CMMI/Safety etc) Audits on need basis.
Participate in Customer-Design meetings and direct customer interactions on need basis.

Key Challenges:

Required to work independently with little supervision.
Requires outstanding communication and leadership skills to ensure effective interaction with program management, engineering management and team members.
The responsible party to business line and engineering management on the delivery of the SoC to production.

Cross functional aspects:

Provide direction, mentoring, and leadership to small to mediumsized groups without direct reporting responsibility.

Your Profile

MS degree desired and BS required in Computer Science, Electrical Engineering or Physics.
Minimum 15 years of experience in the design of subsystems or SoC with prior Chip Lead roles a plus.

Job location:

France