Junior Design Verification Engineer - Sophia Antipolis, France - NXP Semiconductors

NXP Semiconductors

Entreprise vérifiée

Sophia Antipolis, France

il y a 1 semaine

Posté par:

Sophie Dupont

beBee Recruiter

Responsibilities

Responsible for complete functional verification of Sub-System and SOC at all levels presilicon: RTL, PARTL, GLS, PAGLS
Define the verification strategy for the design as a function of its architecture, the expected use cases, the technology the limitations of the tools and the schedule constraints.
Develop, debug, and modify test environments and test cases for different platforms (RTL, PARTL, GLS, PAGLS, Emulation)
Code testcases in an appropriate language (C, SystemVerilog,) and debug these test cases on the design models (RTL, PARTL, GLS, PAGLS, FPGA, Emulation platform)
Work with design and software teams to debug and correct issues or identify workaround. Add additional testcases to verify corrections or workarounds.
Determine the quality of the verification by defining coverage goals and methods for measuring these goals. Enhance the testcases until the goals are met.

Profile

Knowledge of the architecture, elements and functionality of multimedia processor based SOCs (i.

MX, OMAP, EXYNOS), including CPUs, DMA, MMU, PLLS, memory and peripheral interfaces

Knowledge of SoC and IC/IP design processes (Verilog/SystemVerilog)
Understanding of software development process for embedded CPUs and experience in developing and debugging software (C/C++)
Proficient in the languages used for testcase development (C, Verilog, System Verilog,) and scripting (Python)
Expertise in the use of EDA tools for the development, simulation and debug of functional tests (RTL, PART. GLS, PAGLS, NCSIM simulator, C compilers)
Experience with debug on multimedia SoC designs presilicon in simulation.