- Have an expert-level understanding of assigned HW blocks as well as a good understanding of the block in the context of whole system.
- Communicate with architect, designer, algorithm and other verification engineers to lead complex verification tasks, both on module-level and sub-system testing.
- Design complete verification environments.
- Implement design in full UVM environment.
- Perform full block regressions and collection of functional coverage.
- Engineering degree with 3+ years of hands-on experience in ASIC verification using UVM System Verilog
- Experience in unit-level as well as subsystem/full-chip verification.
- Experience working on complex ASIC or SOC designs
- Good knowledge of C/C++ is a plus
- System-Level understanding
- Experience with SOCs in the communications field – advantage
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ASIC Verification Engineer - Paris, France - SEQUANS
Description
PARIS OR SOPHIA ANTIPOLIS, FRANCE – TEL AVIV, ISRAEL
Verification Group in a growing group responsible for pre-silicon ASIC Verification of complex chips implementing an advanced modem technology. As part of the role, you will architect, develop & own blocks / sub-subsystem / system-level verification benches. You will be a major contributor to advanced SV UVM methodologies and to infrastructure development. You will be part of an advanced development flow, using state-of-the-art development & Verification tools and will work closely with the chip architects and RTL / VLSI design teams.
RESPONSIBILITIES
The Verification Engineer will be responsible for different HW blocks at module-level and sub-system level and is expected to:
