- Analyse de spécifications et standardsParticipation à la définition de l'architecture de l'IPCodage RTL (VHDL/Verilog/SystemVerilog)Rédaction et exécution des testbenchs unitairesIntégrationTravail avec l'équipe de vérification pour finalisationRédaction de la documentation technique
- Le design RTL en Verilog et/ou VHDL
- La simulation et les outils associés (ModelSim ou équivalent)
- Les suites Vivado (Xilinx) et/ou Quartus ou d'autres outils équivalents
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Soc-implementation Manager
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Hardware Application Engineer
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Ingénieur FPGA – Design RTL - Provence-Alpes-Côte d'Azur, France - SERMA Ingénierie
Description
Poste et missions
Au sein d'une équipe de spécialistes, vous interviendrez sur un projet pour le développement d'IPs pour la communication sans fil.
Vous aurez en charge la conception d'un ou plusieurs blocs et/ou du top, le design RTL en VHDL/Verilog, l'intégration, la synthèse et la validation.
Vous serez donc impliqué(e) dans différentes étapes du cycle en V, mais principalement sur la partie design :
Profil et compétences
Issu(e) d'une formation Ingénieur/Master 2 en électronique numérique, et vous êtes opérationnel en design RTL (FPGA/ASIC) et justifiez d'au moins 4 ans d'expérience en conception et/ou vérification.
Vous devez maîtriser :
Un connaissance en développement d' IPs Wireless serait apprécié mais n'est pas indispensable.
Anglais courant requis.
Lieu
Le poste est basé à Sophia-Antipolis (06), mais peut également être envisagé à distance.